The present invention relates to a structure production process of a semiconductor device such as a insulated gate type transistor having wiring formed with an aluminum material. The semiconductor device of the invention includes not only a device such as a thin film transistor and a MOS transistor but also an electronic apparatus, such as a display apparatus and an image sensor, having a semiconductor circuit constituted with such an insulated gate type transistor.
In recent years, an active matrix type liquid crystal display having a pixel area and a driving circuit constituted with a thin film transistor (hereinafter abbreviated as TFT) formed on a substrate having an insulating property receives attention. A liquid crystal display includes one having a size of from 0.5 to 2 inches for a projection display and one having a size of from 10 to 20 inches for a portable computer, and is used as a display device of a small size to a middle size.
In recent years, a liquid crystal display having a large area is being demanded. In a liquid crystal display of a large area, the area of a pixel matrix area as an image display part becomes large, and thus source wiring and gate wiring arranged in a matrix form become long, which results in increase in wiring resistance. The wiring should be thin due to a demand of minuteness, and the increase in wiring resistance is tangible. Furthermore, since the source wiring and the gate wiring are connected to a TFT for each pixel, and there arises a problem of increase in parasitic capacity. In a liquid crystal display, since gate wiring and a gate electrode are unitedly formed, delay of a gate signal becomes tangible along with increase in area of the panel.
Accordingly, a material mainly comprising aluminum having a relatively low resistance is used as the gate wiring. By forming the gate wiring and the gate electrode with a material mainly comprising aluminum, the gate delay time can be lowered, and the device can be operated at a high speed.
An attempt of decreasing an off current has been conventionally made by making a thin film transistor having an offset structure or an LDD (light doped drain) structure. In Japanese Patent No. 2,759,415, the inventors propose a thin film transistor of an LDD structure. The Japanese Patent No. 2,759,415 corresponds to a U.S. Pat. No. 5,648,277. The Japanese Patent No. 2,759,415 and the U.S. Pat. No. 5,648,277 disclose a process for forming an LDD structure in a semiconductor layer in a self alignment manner by using aluminum as a gate electrode material and subjecting the gate electrode to anodic oxidation. The process will be described with reference to FIGS. 38A to 38E. An entire disclosure of the Japanese Patent No. 2,759,415 and the U.S. Pat. No. 5,648,277 is incorporated herein by reference.
An underlayer film 1011, such as a silicon oxide film, is formed on a glass substrate 1010. An active layer 1013 comprising a polycrystalline silicon film is formed on the underlayer film 1011,and a gate insulating film 1014 is formed on the active layer 1013. An aluminum film is formed and patterned by using a photoresist mask 1016 to form a gate electrode 1015 comprising aluminum. (FIG. 38A)
The pattern is subjected to anodic oxidation in an electrolytic solution by using the gate electrode 1015 as an anode to form a porous alumina film 1017. In this stage, since the surface of the gate electrode 1015 is covered with the mask 1016, the alumina film 1017 is formed only on the side surface of the gate electrode 1015. (FIG. 38C)
After removing the photoresist mask 1016, the gate electrode 1015 is again subjected to anodic oxidation to form a non-porous alumina film 1018. (FIG. 38B)
The gate insulating film 1014 is patterned by using the alumina films 1017 and 1018 as a mask. (FIG. 38D) The porous alumina film 1017 is then removed.
After obtaining this state, the active layer 1013 is doped with an impurity endowing an n-type or p-type conductivity by a plasma doping method. The doping is conducted as divided into two stages. The first stage is conducted at such low acceleration that the gate insulting film 1014 functions as a mask with a large dose amount. The second stage is conducted at such high acceleration that the impurity passes through the gate insulating film 1014 with a small dose amount. As a result, a channel forming region 80, a source region 81, a drain region 82 and low concentration impurity regions 93 and 84 are formed in the active layer 1013 in a self alignment manner. The low concentration impurity region 84 in the side of the drain region 82 is the LDD region.
However, in order to conduct the anodic oxidation treatment, all the electrodes and wiring to be subjected to anodic oxidation should be connected to voltage supplying wiring for anodic oxidation. For example, in the case where the technique disclosed in the literature described above is applied to an active matrix type liquid crystal panel, the gate electrodes and wiring of the thin film transistor constituting the active matrix area and the driver circuit should be connected to voltage supplying wiring. In order to make such a connection, voltage supplying wiring is formed on the substrate, which results in increase of the area of the substrate.
Each gate electrode and gate wiring forms a short circuit with the voltage supplying wiring, and after the anodic oxidation treatment, unnecessary connected parts to the supplying wiring are removed by etching to separate the respective gate wiring and gate electrodes. Therefore, the circuit should be designed with consideration of a process margin of the etching process.
Accordingly, in order to produce a transistor by using the anodic oxidation treatment, additional area for forming the voltage applying wiring and the etching margin are required, which become a bar to the production of a highly integrated circuit and the decrease in area of the substrate.
Furthermore, since aluminum is used as the material of the gate electrode 1015 in the literature described above, the alumina film 1018 is made of alumina. Therefore, the alumina film should be etched in order to connect the gate wiring and the leading wiring. The inventors have used buffered hydrofluoric acid (a mixed solution of ammonium fluoride and hydrofluoric acid) is used as an etchant on the etching.
However, the buffered hydrofluoric acid is low in selectivity between alumina (representative example thereof is Al2O3) and aluminum, and thus there is a problem in that it etches not only the alumina film but also the gate wiring thereunder. The problem will be described with reference to FIG. 39.
In FIG. 39, numeral 1031 denotes a substrate having an insulating surface, 1032 denotes an insulating film comprising silicon oxide (which functions as a gate insulating film on the active layer), 1033 denotes gate wiring comprising aluminum, 1034 denotes an alumina (anodic oxidized) film obtained by subjecting the gate wiring 1033 to anodic oxidation.
When a part of an upper surface of the alumina film 1034 is etched with the buffered hydrofluoric acid, the gate wiring 1033 is firstly exposed. In general, since the etching is conducted with a certain distribution within the surface of the substrate, it is necessary to completely remove the alumina film 1034 by over-etching.
At this time, when the over-etching is excessively conducted, the gate wiring 1033 is etched by the buffered hydrofluoric acid. There is a possibility that an etching hole 1035 reaches the insulating film 1032 through the gate wiring 1033.
When such a situation is developed, the gate wiring 1033 is connected to the leading line (not shown in the figure) only on a cross section 1036 (expressed by thick lines) of the gate wiring 1033. Because the diameter of the general contact hole is several micrometers, whereas the film thickness of the gate wiring is several hundreds nm, the area on which the gate wiring and the leading line are in contact with each other becomes smaller by about 1/100 than the ordinary case at the state as shown in FIG. 39.
That is, when the situation of FIG. 39 is developed, the contact area of the wiring is extremely decreased to make conditions in that electric contact is impossible. Therefore, the TFT is difficult to be operated, which brings about malfunctioning of the circuit.
When the situation is developed in a structure, in which an active layer of a TFT is present under the insulating film 1032 (for example, contact between the gate electrode and the leading line is made on the TFT), there may be the case in that the leading line and the active layer form a short circuit.
The inventors have then developed a process in that a special etchant is used instead of the buffered hydrofluoric acid. The etchant used by the inventors is an etchant obtained by mixing 10 liter of a solution obtained by mixing phosphoric acid, nitric acid, acetic acid and water in a ratio of 85/5/5/5 with 550 gram of a chromic acid solution (300 gram of chromic acid and 250 gram of water). The inventors call the solution as a chromic mixed acid.
The chromic mixed acid has selectivity in that it etches an alumina film as an anodic oxide film but does not etch an aluminum film. The selective etching of the alumina film can be conducted by using the property of the chromic mixed acid. At present, a contact hole for connecting the gate electrode and the leading line is formed by using such a special etchant. This method realizes a high yield and a good ohmic contact.
However, the method using the chromic mixed acid is not industrially preferred because a large amount of chromium is used, which is a heavy metal that may cause damage to a human body. While development of a substitute etchant is earnestly conducted because of such reasons, a satisfactory etchant has not yet developed at present.
In a TFT using an aluminum material as wiring, when the process temperature after the formation of aluminum wiring is from 300 to 450xc2x0 C., malfunction of the TFT is confirmed. Various factors can be considered as reasons of the malfunction. In particular, many reasons of the malfunction of a TFT are caused by a short circuit between the gate electrode and the channel formed by a protruded matter, such as hillock and whisker, reaching the channel forming region through the gate insulating film, and an aluminum atom being diffused into the gate insulating film.
When aluminum is heated to a temperature of about 400xc2x0 C. hillock is formed on the surface, and an aluminum atom is diffused. Therefore, the heat resistance of aluminum is increased by adding Si and Sc or by subjecting the gate wiring to anodic oxidation to cover an anodic oxide product. In a bottom gate type TFT, the gate wiring must be covered with an anodic oxide film to resist against the film formation temperature of the gate insulating film of from 300 to 450xc2x0 C.
However, in order to conduct the anodic oxidation treatment, all the electrodes and wiring to be subjected to anodic oxidation must be connected to voltage supplying wiring for anodic oxidation. For example, in the case where the technique disclosed in the literature described above is applied to an active matrix type liquid crystal panel, the gate electrodes and wiring of the thin film transistors constituting the active matrix area and the driver circuit must be connected to the voltage supplying wiring. In order to make such a connection, the voltage supplying wiring is formed on the substrate, which results in increase of the area of the substrate.
Each gate electrode and gate wiring forms a short circuit with the voltage supplying wiring, and after the anodic oxidation treatment, unnecessary connected parts to the supplying wiring are removed by etching to separate the respective gate wiring and gate electrodes. Therefore, the circuit should be designed with consideration of a process margin of the etching process.
Accordingly, in order to produce a transistor by using the anodic oxidation treatment, additional area for forming the voltage applying wiring and the etching margin are required, which become a bar to the production of a highly integrated circuit and the decrease in area of the substrate.
Furthermore, a high mobility is demanded in a TFT at present, and a highly crystalline silicon film receives attention as an active layer since it has a higher mobility than an amorphous silicon film. Conventionally, a quartz substrate having a high strain point must be used to obtain a crystalline silicon film by a heat treatment. Since the quartz substrate is expensive, a crystallization technique using an inexpensive glass substrate is being developed.
A technique of lowering the crystallization temperature has been disclosed by the inventors in JP-A-6-232059 and JP-A-7-321339. The JP-A-6-232059 corresponds to a U.S. Pat. No. 5,843,225. An entire disclosure of the JP-A-6-232059, the JP-A-7-321339 and the U.S. Pat. No. 5,843,225 is incorporated herein by reference. In the technique, a slight amount of a metallic element is introduced into an amorphous silicon film, which is then subjected to a heat treatment, to obtain a crystalline silicon film. As the metallic element accelerating the crystallization, at least one selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu and Au is employed. By using this technique, a crystalline silicon film can be produced at a process temperature, to which the glass substrate can resist.
However, the technique involves a problem in that the metallic element used for crystallization remains in the crystalline silicon film, which may be a cause of deterioration of the reliability and uniformity in characteristics of the TFT. The inventors have then developed a technique in that after forming wiring by using an aluminum material, the metallic element contained in the crystalline silicon film is gettered (JP-A-8-330602). An entire disclosure of the JP-A-8-330602 is incorporated herein by reference. In this technique, a heat treatment is conducted by using the source/drain region as a gettering sink, and thus the metallic element contained in the channel forming region is gettered to the source/drain region.
However, since the gettering technique described above employs an aluminum material having a low heat resistance as wiring, only the heat treatment at a temperature range of about from 300 to 450xc2x0 C. is conducted. The heating temperature of from 300 to 450xc2x0 C. is too low to sufficiently conduct gettering of the metallic element contained in the crystalline silicon film, and a treatment for a long period of time is necessary. Therefore, the short circuit between the gate electrode and the channel described above is liable to occur.
As a method for forming the crystalline silicon film, a method for forming a polycrystalline silicon film by as-depo, and a method for crystallizing an amorphous silicon film by a heat treatment or irradiation with laser light have been known.
In the case of a bottom gate type TFT, the gate wiring is formed before the formation of the active layer. Therefore, a crystallization process using an excimer laser is preferred for making small the influence of heat to the gate wiring. In the case where an aluminum material is used as the gate wiring, even when the laser crystallization process is employed, and the heat resistance is increased by the anodic oxidized film, there may be the case where the gate wiring is deformed due to the formation of a protruded matter, such as hillock and whisker, on aluminum.
As described in the foregoing, the uses of an aluminum material for wiring from the standpoint of wiring resistance, but various problems arise by using the aluminum material. The problems are summarized below.
First, a thin film transistor having an LDD structure can be produced in a self alignment manner by using the anodic oxidation technique. However, because voltage supplying wiring for anodic oxidation must be formed, high integration of the circuit and decrease in area of the substrate are inhibited.
Second, in a process for forming a contact hole for a leading electrode of a gate electrode, the use of the chromic mixed acid is unavoidable for removing alumina covering the gate electrode.
Third, because of the low heat resistance of aluminum, a short circuit is formed between gate wiring and a channel, to cause malfunction of the TFT.
Furthermore, in a bottom gate type TFT, the gate wiring is formed before the crystallization process of the silicon film. In the total process, the crystallization process is one applying the largest heat influence to the gate wiring. Even when a laser crystallization process applying a relatively small heat influence is employed, and the aluminum layer is covered with the anodic oxide film, it is difficult to completely prevent deformation (blister) of the gate wiring due to the formation of hillock.
The invention relates to a semiconductor device having a novel wiring structure that solves the problems described above at a stroke.
In the invention, the anodic oxidization of an aluminum material is conducted without forming voltage supplying wiring for anodic oxidation. Furthermore, a first wiring comprising a laminated structure of alumina and aluminum, and good ohmic contact between the first wiring and a second wiring electrically contacting with the first wiring are realized without using the chromic mixed acid, and a short circuit between the gate electrode and the channel is prevented.
In order to solve the problems described above, the invention relates to a semiconductor device having wiring comprising a laminated structure comprising a first wiring layer comprising a first conductive film having laminated thereon a second wiring layer comprising a second conductive film, wherein the wiring comprises a first oxide film formed by oxidizing the first wiring layer, and a second oxide film formed by oxidizing the second wiring layer; a lower part of the second wiring layer is in contact only with the first wiring layer; and a lower part of the second oxide film is in contact with the first wiring layer and the first oxide film.
One of the characteristic features of the invention resides in the wiring having the multi-layer structure, in which diffusion of the material constituting the second wiring layer is prevented by the first wiring layer. Therefore, the upper limit of the process temperature after the formation of the gate wiring can be increased. Another characteristic feature of the invention is to conduct anodic oxidation of the first and second wiring layers without forming voltage supplying wiring for anodic oxidation. Accordingly, by using the first conductive film constituting the first wiring layer as the wiring for anodic oxidation, anodic oxidation of the second wiring layer is realized.
The path to the invention will be described with reference to FIGS. 35A to 35E, 36A to 36C, 37A to 37C and 38A to 38E.
The inventors have confirmed as to whether or not plural aluminum patterns formed on a tantalum film by patterning to an island form can be subjected to anodic oxidation by using the tantalum film as an electrode. FIGS. 35A to 35E are cross sectional views showing the aluminum pattern in each steps of the experiment. FIGS. 36A to 36C are partial enlarged cross sectional view of FIGS. 35C to 35E. FIGS. 37A to 37C are SEM (Scanning Electron Microscope) photographs obtained by observing the cross sectional structures in FIGS. 36A to 36C.
The experiment was conducted in the following manner.
A tantalum (Ta) film 41 having a thickness of 20 nm and an aluminum (Al) film 42 having a thickness of 400 nm were formed on a glass substrate 40 (5-inch square, Glass Substrate 1737 produced by Corning, Inc.) by a sputtering method. The surface of the aluminum film 42 was subjected to anodic oxidation by connecting a probe of an anodic oxidation apparatus to the aluminum film, to form an anodic oxide film 49 of a barrier type. The barrier type anodic oxide film (hereinafter expressed as barrier A.O. film) was alumina. (FIG. 35A)
The anodic oxidation was conducted by using an ethylene glycol solution containing 3% of tartaric acid as an electrolytic solution under the conditions of a solution temperature of 30xc2x0 C., an ultimate voltage of 10 V, a voltage application time of 15 minutes and a supplied electric current of 10 mA per one substrate. The anodic oxidation step was conducted to increase adhesion of a resist mask 59. The anodic oxidation step is called a mask anodic oxidation step since the barrier A.O. film 49 is formed on the surface of the Al film 42.
A resist mask 59 is then formed, and the A.O. film 49 and the Al film were etched to form plural patterns 43 of gate wiring comprising the Al film (hereinafter expressed as gate Al 43). The gate Al 43 were formed in the form separated for each wiring. In FIG. 34B, only 2 of the gate Al 43 are shown.
An acid obtained by mixing 10 liter of a solution obtained by mixing phosphoric acid, nitric acid, acetic acid and water in a ration of 85/5/5/5 with 550 gram of a chromic acid solution (300 gram of chromic acid and 250 gram of water) was used as an etchant for the barrier A.O. film 49. The etchant is called as a chromic mixed acid. An acid obtained by mixing phosphoric acid, nitric acid, acetic acid and water in a ration of 85/5/5/5 was used as an etchant for the Al film 42. The etchant is called as an aluminum mixed acid. (FIG. 35B)
While the resist mask 59 remained, anodic oxidation was conducted by applying a voltage to the Ta film 41 in the anodic oxidation apparatus. The anodic oxidation was conducted by using a 3% oxalic acid aqueous solution as an electrolytic solution under the conditions of an ultimate voltage of 8 V, a voltage application time of 40 minutes and a supplied electric current of 20 mA per one substrate. In the case where the conventional anodic oxidation method using these anodic oxidation conditions, a porous type anodic oxide (porous A.O.) 44 is formed on a side surface of the aluminum pattern 43. The anodic oxidation step is then called as a side anodic oxidation step. (FIG. 35C)
After removing the resist mask 59, anodic oxidation was again conducted by applying a voltage to the Ta film 41 in the anodic oxidation apparatus. The anodic oxidation was conducted by using an ethylene glycol solution containing 3% of tartaric acid as an electrolytic solution under the conditions of an electrolytic solution temperature of 10xc2x0C., an ultimate voltage of 80 V, a voltage application time of 30 minutes and a supplied electric current of 30 mA per one substrate. In the case where the conventional anodic oxidation method using these anodic oxidation conditions, tartaric acid penetrates into the porous A.O. film 44, and the surface of the gate Al film 43 is subjected to anodic oxidation to form a barrier type anodic oxide (barrier A.O.) film 46. Thus, the anodic oxidation step is called as a barrier anodic oxidation step. The barrier A.O. film 46 comprised non-porous alumina. (FIG. 35D)
The porous A.O. film 44 was removed by wet etching using the aluminum mixed acid. (FIG. 35E)
The results and discussions of the experiment will be described below. In order to confirm as to whether the Ta film 41 functioned as voltage supplying wiring for anodic oxidation, the sheet resistance of the Ta film 41 was measured in each steps. Further, after each steps of FIGS. 35C to 35E, the cross sectional structure was observed by the SEM. FIGS. 37A to 37C show the SEM photographs. FIGS. 36A to 36C schematically show the SEM photographs, and the cross sectional views of FIGS. 37A to 37C correspond to FIGS. 36A to 36C, respectively. In FIGS. 36A to 36C and 37A to 37C, the same names and the same symbols correspond to the constitutional elements in FIGS. 35A to 35E.
The sheet resistance of the Ta film 41 in the initial stage (before the mask anodic oxidation step) was 100.1 xcexa9 per square. The sheet resistance after the side anodic oxidation step was 205.1 xcexa9 per square, and that after the completion of the barrier anodic oxidation step was a value exceeding the measurable range of the measuring device used. The maximum value of the measurable value of the device was 5,000 kxcexa9 per square, and it could be considered that the sheet resistance after the completion of the barrier anodic oxidation step was at least 5,000 kxcexa9 per square.
The glass substrate 40 was observed with the naked eyes after the completion of the side anodic oxidation step, and it was found that the transparency of the Ta film 41 was increased in comparison to the initial stage. It could be expected from this and the sheet resistance that the Ta film 41 was slightly oxidized by oxalic acid. The film thickness of the Ta film 41 suffered substantially no change in the SEM photograph of FIG. 35A, and thus it was understood that the Ta film 41 suffered substantially no oxidation. Furthermore, it was observed that the gate Al 43 divided into an island form was subjected to anodic oxidation by applying a voltage to the Ta film 41, to form the porous A.O. (porous alumina). (FIG. 36A)
Similarly, the glass substrate 40 was observed with naked eyes after the completion of the barrier anodic oxidation step, and it was found that the exposed Ta film 41 was substantially transparent. This was because tartaric acid used for the mask anodic oxidation step also anodically oxidized tantalum, and it was expected that the Ta film 41 at that part was modified to a tantalum oxide film 45 (hereinafter expressed as a TaOx film) by the anodic oxidation.
According to the SEM observation photograph of FIG. 35B, in which the film thickness of the Ta film 41 under and outside the porous A.O. film 44 became three times, it was understood that the Ta film 41 had been subjected to anodic oxidation to become a TaOx film 45 in these parts. It is understood from the fact that the sheet resistance value became extremely large.
However, since tantalum oxide is an insulating material, there arises a problem in that whether the TaOx film 45 functions as wiring. Because the electric current value monitored during the barrier anodic oxidation step did not exhibit large fluctuation, it was considered that a voltage was applied to the gate Al 43 even though the Ta film 41 was modified to the TaOx film 45. It is expected that this is because although the TaOx film 45 has an extremely large sheet resistance, the oxygen content thereof is smaller than Ta2O5 (tantalum pentaoxide), the stoichiometric ratio, and thus it exhibits a slight conductivity (semi-insulating property). It is considered that the deviation from the stoichiometric ratio is largely ascribed to the fact that the TaOx film 45 is formed by anodic oxidation.
Then, the cross sectional structure was observed to confirm as to whether or not the barrier A.O. film 46 was formed to cover the gate Al 43. (FIG. 36C and FIG. 37C)
The aluminum mixed acid was used in the etching process of FIG. 35E. The aluminum mixed acid etches both the porous alumina (porous A.O. film 44) and the aluminum, but substantially does not etch non-porous alumina (barrier A.O. film 46). Therefore, when the barrier A.O. film 46 is not sufficiently formed in the barrier anodic oxidation step, the gate Al 43 is also removed.
In the SEM observation photograph of FIG. 37C, it is confirmed that the gate Al 43 remains after the etching treatment with the aluminum mixed acid. Therefore, it is concluded that the barrier A.O. film 46 that can withstand the aluminum mixed acid in the mask anodic oxidation step. Under the conditions of this experiment, the film thickness of the barrier A.O. film 46 is about 100 nm. In this process, the barrier A.O. films 46 and 49 are substantially united.
Through the experiment described above, it has been found that the gate Al 43 can be subjected to anodic oxidation by applying a voltage to the Ta film 41 under the conditions in that the Ta film 41 formed on the whole surface of the glass substrate 40 and the gate Al 43 selectively formed thereon form a short circuit. In particular, it has been found that when the Ta film 41 is used as the voltage supplying wiring for anodic oxidation using tartaric acid, the gate Al 43 formed thereon can be subjected to anodic oxidation.
It is understood from the comparison between the photographs of FIGS. 37B and 37C that the film thickness distribution of the TaOx film 45 is different between the region on which the A.O. films 44 and 46 are present and the region on which the A.O. films 44 and 46 are not present.
In the barrier anodic oxidation step, an exposed part of the Ta film 41 is in direct contact with tartaric acid and is subjected to anodic oxidation. Since the porous A.O. film 44 is of porous nature, tartaric acid penetrates therein. The anodic oxidation of the Ta film 41 proceeds under the porous A.O. film 44, and simultaneously the anodic oxidation of the gate Al 43 proceeds on the side surface of the porous A.O. film 44.
However, due to the difference in anodic oxidation rate, the interface between the gate Al 43 and the A.O. film 46 is present inside the interface between the Ta film 41 and the TaOx film 45 as shown in FIG. 36B. Therefore, the lower part of the barrier A.O. film 46 is in contact with both the Ta film 41 and the TaOx film 45, and the lower part of the gate Al 43 is in contact with only the Ta film 41.
Because the TaOx film 45 and the barrier A.O. film 46 are formed by the same anodic oxidation step, it is considered that the interface between the TaOx film 45 and the barrier A.O. film 46 and the vicinity thereof become an oxide of alloy comprising Ta and Al. Since the TaOx film 45 is formed to push up the barrier A.O. film 46, it exhibits excellent adhesion to the barrier A.O. film 46. Since the edge of the interface between the barrier A.O. film 46 and the Ta film 41 is sealed with the TaOx film 45, an effect of preventing the diffusion of Al from the gate Al 43 is highly exhibited.
With respect to the film thickness of the TaOx film 45 under the A.O. film 46 denoted by a region 61, the thickness t1 is gradually decreased toward the Ta film 41. While the thickness is gradually increased from the region 61 toward the outside of the A.O. film 46, the film thickness t2 becomes the maximum under the porous A.O. film 44 at a part 62. The thickness is gradually decreased from the part 62 toward the outside, and the film thickness t3 becomes substantially constant in a region 63.
The TaOx film 45 at a part extending from the side surface of the barrier A.O. film 46 is formed by anodic oxidation under the conditions in that the porous A.O. film 44 is present. Therefore, it is considered that the surface layer of the TaOx film 45 at this part becomes an oxide compound of an alloy comprising Ta and Al due to the reaction with the porous A.O. film 44.
The film thickness of the TaOx film 45 is summarized below. The film thickness is different between the part under the barrier A.O. film 46 and the part under the porous A.O. film 44. The film thickness under the barrier A.O. film 46 is gradually increased from the interface to the Ta film 41 toward the outside. In the part under the porous A.O. film 44, the part 62 exhibiting the maximum film thickness t2 and the region 63 exhibiting the constant thickness t3 are present. In the region on which the A.O. films 44 and 46 are not present, only the region 63 exhibiting the constant thickness t3 is present. Since when Ta is oxidized, the thickness thereof is increased by 2 times to 4 times, the film thickness t2 and t3 are from 2 times to 4 times the thickness of the Ta film 41.
The constitution of the invention is based on the knowledge obtained from the experimental results described above. In the invention, the second wiring layer is formed on the first conductive film in such a manner that the second wiring layer is electrically separated by the respective wiring, and the second wiring layer is subjected to anodic oxidation by applying a voltage to the first conductive film under the conditions in that the plural second wiring layers form a short circuit by the first conductive film.
In the constitution described above, the second wiring layer as an upper layer is mainly used as a path of electric charge, and the film thickness thereof is about from 200 to 500 nm. It is preferred that the conductive film constituting the second wiring layer comprises aluminum or a material mainly comprising aluminum, to lower the resistance of the wiring.
A valve metal can be used as the first conductive film. The valve metal is a metal exhibiting a function like a valve, i.e., a barrier type anodic oxide film formed anodically passes a cathode electric current but does not pass an anode electric current. We quoted the description of the valve metal from xe2x80x9cElectrochemistry Handbook, 4th Ed., Society of Electrochemistry, page 370, Maruzen (1985)xe2x80x9d.
Examples of the valve metallic film having a melting point higher than aluminum include tantalum (Ta), niobium (Nb), hafnium (Hf), zirconium (Zr), titanium (Ti) and chromium (Cr). Furthermore, as the first conductive film, an alloy containing the valve metallic element, such as molybdenum tantalum (MoTa) can be employed.
Particularly, it has been confirmed that tantalum can be subjected to anodic oxidation in the same electrolytic solution as a thin film mainly comprising aluminum, and tantalum is preferably used in the invention. A tantalum alloy, such as molybdenum tantalum (MoTa), and tantalum nitride (TayN (y greater than 1)), as tantalum containing nitrogen, can be employed. Furthermore, these conductive materials have a melting point higher than aluminum, and exhibit a blocking function of preventing diffusion of aluminum element.
While it is preferred that the thickness of the first conductive film is as thin as possible, such a thickness is required that can function as a blocking layer of preventing diffusion of the constitutional element of the second wiring layer. The thickness of the first conductive film is 1 nm or more, and preferably 5 nm or more.
It is considered that the upper limit of the film thickness of the first conductive film is 50 nm, and preferably about 30 nm. The first oxide is formed by oxidizing the first conductive film, and the thickness thereof becomes 2 times to 4 times the thickness of the first conductive film. Therefore, the upper limit of the film thickness of the first conductive film is 50 nm, and preferably 30 nm taking the throughput of the film formation of the first conductive film and the etching of the first oxide into consideration. In the case where an aluminum film is used as the second conductive film, and a tantalum film is used as the first conductive film as an underlayer, when the thickness of the tantalum film is 20 nm or 50 nm, it has been confirmed that aluminum is not diffused into the lower layer of the tantalum film even though the wiring is subjected to a heat treatment at 550xc2x0 C.
It is considered from the above that the film thickness of the first conductive film is selected from the range of from 1 to 50 nm (preferably from 5 to 30 nm, and more preferably from 5 to 20 nm).